Cooperative Caching for Chip Multiprocessors
By Jichuan Chang, G. Sohi. International Symposium on Computer Architecture, 2006
424 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/fd4761b9c51bca0d20c39226e25747dbcf022013
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Doug Burger
- Naveen Muralimanohar
- Rajeev Balasubramonian
- Moinuddin K. Qureshi
- Yale N. Patt
- N. Jouppi
- S. Keckler
- Lixin Zhang
In Hardware and Architecture
- Rajeev Balasubramonian
- Doug Burger
- Naveen Muralimanohar
- Moinuddin K. Qureshi
- Sangyeun Cho
- Yale N. Patt
- Onur Mutlu
- S. Keckler
Citations in the corpus
- Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (2006, background): “Recent proposals [3][1] have looked at dynamic mechanisms to obtain the hit latency of a private cache while approximating the capacity benefits of a shared cache.”
- Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, background): “Examples of ongoing research in these veins include [5, 6, 10, 11, 12, 15, 19, 20, 21, 22, 33, 44].”
- Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006, background): “Researchers are actively exploring the L2 cache design space to tackle this problem [8,9,12,21,30].”
- A NUCA Substrate for Flexible CMP Cache Sharing (2007, background): “designs are based on a shared L2 cache, Cooperative Caching [5] uses private caches as the baseline design and adopts the benefits of a shared cache by using cache-tocache transfers and modifying cache replacement policies.”