Smart Memories: a modular reconfigurable architecture

By K. Mai, T. Paaske, Nuwan Jayasena, R. Ho, William (Bill) J. Dally, Mark A. Horowitz. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

496 citations recorded by the source corpus.

Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, targeted at computing needs in the 0.1 /spl mu/m technology generation. A Smart Memories chip is made up of many processing tiles, each containing local memory, local interconnect, and a processor core. For efficient computation under a wide class of possible applications, the memories, the wires, and the computational model can all be altered to match the applications. To show the applicability of this design, two very different machines at opposite ends of the architectural spectrum, the Imagine stream processor and the Hydra speculative multiprocessor, are mapped onto the Smart Memories computing substrate. Simulations of the mappings show that the Smart Memories architecture can successfully map these architectures with only modest performance degradation.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/28ce7bf8e2e62151038f20237722a9613d95f0ad

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Citations in the corpus

PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture (2015, background): “To date, most of the existing PIM architectures are based on general-purpose computation units inside memory for ﬂex-ibility across different applications [14–16,25,28,35,39–41, 46, 48, 50].”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “Processing-in-memory has been proposed for at least four decades [39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53].”
A highly configurable cache architecture for embedded systems (2003, background): “Smart memory [17] is a modular reconfigurable architecture, which is made up of many processing tiles, each containing local memories and processor cores, which can be altered to match the different applications.”
StreamIt: A Language for Streaming Applications (2002, background): “Also, we believe that StreamIt is a viable common machine language for grid-based architectures (e.g., [ 4 ,5,6]), just as C is a common machine language for von-Neumann machines.”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, background): “Later works [29, 79, 95, 112] propose more versatile substrates that increase the flexibility and computational capability available within the DRAM chip.”
A stream compiler for communication-exposed architectures (2002, unknown): “INTRODUCTION As we approach the billion-transistor era, a number of emerging architectures are addressing the wire delay prob- lem by replicating the basic processing unit and exposing the communication between units to a software layer (e.g., Raw [33], SmartMemories [22], TRIPS [28]).”
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (2015, methodology): “This motivates us to re-examine the previous processors-inmemory (PIM) architectures [3–10] that aimed to improve performance by integrating processor logic and DRAM on the same die.”
Core fusion: accommodating software diversity in chip multiprocessors (2007, methodology): “This alone would set core fusion apart from other proposed reconfigurable architectures, such as TRIPS [37] or Smart Memories [28], and from speculative architectures such as”
Clock rate versus IPC: the end of the road for conventional microarchitectures (2000, background): “This observation is not new; a number of researchers and product teams have proposed or implemented partitioned architectures [8, 9, 10, 12, 15, 21, 25, 29].”
The future of wires (2001, background): “variety of programming models efficiently [53].”
A high throughput string matching architecture for intrusion detection and prevention (2005, background): “Another example where the optimizations we present would still be valuable is where the application is mapped down to more general purpose programmable memory tiles [18, 29, 27].”