Giovanni De Micheli
Computer Networks and Communications · 2000–2015
A researcher in the Science corpus: 11 papers; trusts 14 researchers and is trusted by 34 researchers here, as inferred from the citation graph.
Subfields
- Computer Networks and Communications — 25 citations into it; #754 of 9,886 by trust here, #1,370 by citations
- Hardware and Architecture — 22 citations into it; #47 of 1,551 by trust here, #161 by citations
- Electrical and Electronic Engineering — 9 citations into it; #1,064 of 16,539 by trust here, #4,807 by citations
Whom Giovanni De Micheli trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
- Luca Benini
- Jingcao Hu
- Hangsheng Wang
- Martin L. Puterman
- Shashi Kumar
- William (Bill) J. Dally
- K. Mai
- Radu Marculescu
Who trusts Giovanni De Micheli overall
- Ümit Y. Ogras
- Radu Marculescu
- Srinivasan Murali
- Jingcao Hu
- Davide Bertozzi
- Vasilis F. Pavlidis
- Ming Li
- Tobias Bjerregaard
- Evgeny Bolotin
- Mikael Millberg
Papers from Giovanni De Micheli's perspective
Ordered by how strongly the researchers Giovanni De Micheli trusts endorse each paper. Same corpus, a different order for every researcher.
- Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
- Networks on Chips: A New SoC Paradigm (Computer)
- Addressing the system-on-a-chip interconnect woes through communication-based design (Proceedings - Design Automation Conference)
- A network on chip architecture and design methodology (Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002)
- A generic architecture for on-chip packet-switched interconnections (Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537))
- The future of wires (Proceedings of the IEEE)
- Theory of latency-insensitive design (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.)
- Bandwidth-constrained mapping of cores onto NoC architectures (Proceedings Design, Automation and Test in Europe Conference and Exhibition)
- Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (2003 Design, Automation and Test in Europe Conference and Exhibition)
- SUNMAP: a tool for automatic topology selection and generation for NoCs (Proceedings - Design Automation Conference)
Their papers
- Networks on Chips: A New SoC Paradigm (2002) — 4,067 citations
- SUNMAP: a tool for automatic topology selection and generation for NoCs (2004) — 349 citations
- Analysis of power consumption on switch fabrics in network routers (2002) — 484 citations
- A survey of design techniques for system-level dynamic power management (2000) — 1,347 citations
- The EPFL Combinational Benchmark Suite (2015) — 452 citations
- Networks on Chips: Technology and Tools (2006) — 524 citations
- Analysis of error recovery schemes for networks on chips (2005) — 349 citations
- NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005) — 621 citations
- Bandwidth-constrained mapping of cores onto NoC architectures (2004) — 756 citations
- Networks on chip: a new paradigm for systems on chip design (2002) — 379 citations
- System-level power optimization: techniques and tools (2000) — 392 citations