Three-dimensional integrated circuits

By Anna W. Topol, D. L. Tulipe, Leathen Shi, D. Frank, K. Bernstein, S. Steen, Arvind Kumar, G. Singco, A. Young, Kathryn W. Guarini and 1 more. IBM Journal of Research and Development, 2006

718 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/8de20d9e01b189c02f5e68ae3720965bed48c82c

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In Electrical and Electronic Engineering

Citations in the corpus

Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems (2011, neutral): “density [16], [17] on a smaller footprint.”
Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs (2010, background): “The fabrication of 3-D stacked IC (SIC) involves stacking of one or more chips, and the through silicon via (TSV) [2] constitutes a key component for interconnecting chips vertically and forms a cylindrical metal–oxide–semiconductor (MOS) capacitor with the semiconductor substrate acting as the bulk”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, background): “Upcoming 3D processes have a finite number of layers due to manufacturing difficulties and yield issues [7].”
Wafer-Level Heterogeneous Integration for MOEMS, MEMS, and NEMS (2011, background): “The general advantage of via-last approaches is that they enable the implementation of extremely small vias with diameters of below 1 μm [102].”
A study of thermo-mechanical stress and its impact on through-silicon vias (2008, background): “Vertical or three-dimensional (3D) chip integration is one of the core approaches under investigation to achieve smaller package size, reduced power consumption and higher device speed [1].”
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology (2009, neutral): “wafer to enable communication among the stacked chips [1],”
Three-dimensional silicon integration (2008, background): “SSI technology and module integration SSI investigations for 3D circuit integration have ranged from studies of SOI structures [20], to thin die stacks using face-to-face or face-to-back structures [38, 39], to silicon stacking [44], and silicon-on-silicon packages [21, 45, 46].”
Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits (2014, neutral): “[20].”
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits (2010, methodology): “New silicon-based technologies such as FinFET devices [2] and 3-D integration [ 3 ] provide a path to increasing transistor counts in a given footprint.”
3D silicon integration (2008, background): “SOI to few microns silicon thickness, respectively [11, 12], (ii) 1 to 20 um diameter or width and silicon thickness of a”