Srinivasan Murali

Computer Networks and Communications · 2004–2005

A researcher in the Science corpus: 4 papers; trusts 11 researchers and is trusted by 7 researchers here, as inferred from the citation graph.

Subfields

• Computer Networks and Communications — 27 citations into it; #2,403 of 9,886 by trust here, #4,594 by citations
• Hardware and Architecture — 24 citations into it; #283 of 1,551 by trust here, #731 by citations
• Electrical and Electronic Engineering — 10 citations into it; #6,303 of 16,539 by trust here, #14,379 by citations

Whom Srinivasan Murali trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. Luca Benini
2. Giovanni De Micheli
3. Jingcao Hu
4. Hangsheng Wang
5. Shashi Kumar
6. Radu Marculescu
7. K. Mai
8. Kees G. W. Goossens
9. Xinping Zhu
10. Axel Jantsch

Who trusts Srinivasan Murali overall

1. Ümit Y. Ogras
2. Radu Marculescu
3. Jingcao Hu
4. Davide Bertozzi
5. Antoine Jalabert
6. Tobias Bjerregaard
7. Pradip Kumar Sahu
8. Li-Shiuan Peh

Papers from Srinivasan Murali's perspective

Ordered by how strongly the researchers Srinivasan Murali trusts endorse each paper. Same corpus, a different order for every researcher.

1. Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
2. Networks on Chips: A New SoC Paradigm (Computer)
3. Addressing the system-on-a-chip interconnect woes through communication-based design (Proceedings - Design Automation Conference)
4. A network on chip architecture and design methodology (Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002)
5. A generic architecture for on-chip packet-switched interconnections (Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537))
6. Theory of latency-insensitive design (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.)
7. Bandwidth-constrained mapping of cores onto NoC architectures (Proceedings Design, Automation and Test in Europe Conference and Exhibition)
8. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (2003 Design, Automation and Test in Europe Conference and Exhibition)
9. SUNMAP: a tool for automatic topology selection and generation for NoCs (Proceedings - Design Automation Conference)
10. System-level design: orthogonalization of concerns andplatform-based design (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.)

Their papers

• SUNMAP: a tool for automatic topology selection and generation for NoCs (2004) — 349 citations
• Analysis of error recovery schemes for networks on chips (2005) — 349 citations
• NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005) — 621 citations
• Bandwidth-constrained mapping of cores onto NoC architectures (2004) — 756 citations