Core fusion: accommodating software diversity in chip multiprocessors

By Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez. International Symposium on Computer Architecture, 2007

321 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/2f24530afc1c49f07ff6a2403782638d99b17821

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Citations in the corpus

Thread motion: fine-grained power management for multi-core systems (2009, methodology): “We leverage the existing MESI coherence protocol to handle on-demand transfer of data using the shared-L2 cache for applications that move (similar to [10]).”
Accelerating critical section execution with asymmetric multi-core architectures (2009, background): “[21] propose Core Fusion, where multiple small cores can be combined, i.”
Effective Straggler Mitigation: Attack of the Clones (2013, unknown): “, [30, 31, 32, 33, 34]), datacenters periodically check for faulty machines and avoid scheduling jobs on them.”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “Core Fusion [63] and CLPs [64] are dynamically configurable chip multiprocessors that a group of”
Dark silicon and the end of multicore scaling (2011, background): “Composed Multicore: The composed multicore topology consists of a collection of small cores that can logically fuse together to compose a high-performance large core for the execution of the serial portion of code [17, 19].”
The multikernel: a new OS architecture for scalable multicore systems (2009, background): “Some will have the same instruction set architecture (ISA) but different performance characteristics [34,59], since a processor with large cores will be inefficient for readily parallelized programs, but one using only small cores will perform poorly on the sequential parts of a program [31,42].”