Design and Management of 3D Chip Multiprocessors Using Network-in-Memory

By Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut Taylan Kandemir. International Symposium on Computer Architecture, 2006

426 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials

View Paper: https://www.semanticscholar.org/paper/2ae11d565e0016332914d619c8a91c3b6f00148d

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In Computer Networks and Communications

In Electrical and Electronic Engineering

In Electronic, Optical and Magnetic Materials

Partha Pratim Pande

Citations in the corpus

A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, methodology): “In addition, hybridization of 2D NoC routers with TSBs require one (instead of two) additional link on each NoC router, because TSB can move data both upward and downward [20].”
Cooperative Caching for Chip Multiprocessors (2006, background): “We have presented cooperative caching as a uniﬁed approach to manage a CMP’s aggregate on-chip cache resources.”
3D-ICE: Fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling (2010, background): “…martino.ruggiero, david.atienza}@ep..ch, tbr@zurich.ibm.com ABSTRACT Three dimensional stacked integrated circuits (3D ICs) are extremely attractive for overcoming the barriers in interconnect scaling, o.ering an opportunity to continue the CMOS performance trends for the next decade.”
3-D Topologies for Networks-on-Chip (2006, background): “…for a single line of a crossbar switch , horizontal buss , and vertical buss is, respectively, (22) (23) (24) The power consumption of the arbitration logic does not appear in (22)–(24), since most of the power is consumed by the crossbar switch and the buss interconnect, as discussed in [32].”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, methodology): “For consistency with [12], our analysis considers the use of a dynamic, time-division multiple-access (dTDMA) bus, although any other type of bus may be used as well.”
Hybrid cache architecture with disparate memory technologies (2009, background): “Previous work focuses on the performance improvement and power reduction by stacking cache or main memory on top of processors [6, 18, 19, 20].”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, background): “Examples of ongoing research in these veins include [5, 6, 10, 11, 12, 15, 19, 20, 21, 22, 33, 44].”