Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

By Kern Rim, K. K. Chan, Leathen Shi, D. Boyd, John A. Ott, N. Klymko, F. Cardone, L. Tai, Steven J. Koester, M. Cobb and 10 more. IEEE International Electron Devices Meeting 2003, 2003

171 citations recorded by the source corpus.

Subfields: Biomedical Engineering, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/386370d930ae91a7589e0e9a048ef3af7610baea

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In Biomedical Engineering

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Citations in the corpus

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor (2011, methodology): “The strain in an SDGTFET is controlled by the Ge mole-fraction (x) that has been used to fabricate the sSOI [25-27].”
Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions (2008, background): “In practice, a biaxially strained Si (originally pseudomorphic to a relaxed SiGe layer with 50% Ge and transferred) directly on insulator substrate [10]‐[ 12 ] could be used, and the strained Ge source region can be produced by selective epitaxial growth.”
Uniaxial-process-induced strained-Si: extending the CMOS roadmap (2006, background): “To date, unlike biaxial stress [48], limited data exist for the maximum mobility possible for uniaxial stress.”
A 90-nm logic technology featuring strained-silicon (2004, result): “For low to moderate biaxial stress, the piezoresistance coefficient predicts a slight mobility degradation which is consistent with the biaxial stress experimental data [19], [20] (see Fig.”
Review: Semiconductor Piezoresistance for Microsystems (2009, background): “groups [385]–[387] and noted that ‘‘the hole mobilities of Ge and GaAs”
Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs (2004, background): “Alternatively, electron mobility enhancement can be obtained using longitudinal uniaxial tensile stress typically introduced with a nitride capping layer [5], [10], [11].”
Silicon CMOS devices beyond scaling (2006, background): “Strained-silicon technology [13, 47], for instance, is an example of the former.”
Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers (2006, methodology): “We also show data from Rim et al. [ 27 ] and Leitz et al. [28] for comparison.”
Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance (2008, unknown): “bulk strained-Si/relaxed-SiGe [48], [50]–[61], strained-Si/ SiGe-on-insulator (SGOI) [62]–[68], and single strainedsilicon-on-insulator (SOI) substrates [69]–[71], has already”