M. Stettler

Electrical and Electronic Engineering · 2000–2006

A researcher in the Science corpus: 4 papers; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.

Subfields

Whom M. Stettler trusts

Their strongest outbound trust, strongest first, inferred from their citations.

  1. Massimo V. Fischetti (in Electrical and Electronic Engineering)

Papers from M. Stettler's perspective

Ordered by how strongly the researchers M. Stettler trusts endorse each paper. Same corpus, a different order for every researcher.

  1. Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs (IEEE International Electron Devices Meeting 2003)
  2. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors (IEEE International Electron Devices Meeting 2003)
  3. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors
  4. Long-range Coulomb interactions in small Si devices. Part II. Effective electron mobility in thin-oxide structures
  5. Hole mobility enhancements and alloy scattering-limited mobility in tensile strained Si/SiGe surface channel metal-oxide-semiconductor field-effect transistors
  6. Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness
  7. Device scaling limits of Si MOSFETs and their application dependencies (Proceedings of the IEEE)
  8. Limits to binary logic switch scaling - a gedanken model (Proceedings of the IEEE)
  9. Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm (Digest. International Electron Devices Meeting,)
  10. Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs

Their papers