Mark T. Bohr

Electrical and Electronic Engineering · 2000–2005

A researcher in the Science corpus: 7 papers; trusts 7 researchers and is trusted by 1 researcher here, as inferred from the citation graph.

Subfields

• Electrical and Electronic Engineering — 17 citations into it; #13,956 of 16,539 by trust here, #5,309 by citations

Whom Mark T. Bohr trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. Yu Huang
2. Xiangfeng Duan
3. Stefan K. Lai
4. Yi Cui
5. Cees Dekker

Who trusts Mark T. Bohr overall

1. George M. Whitesides
2. Johannes Barth
3. Babak A. Parviz

Papers from Mark T. Bohr's perspective

Ordered by how strongly the researchers Mark T. Bohr trusts endorse each paper. Same corpus, a different order for every researcher.

1. Six-band k⋅p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness
2. Device scaling limits of Si MOSFETs and their application dependencies (Proceedings of the IEEE)
3. OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications (International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224))
4. Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs (IEEE International Electron Devices Meeting 2003)
5. Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs (2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303))
6. Ultrathin high-K gate stacks for advanced CMOS devices (International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224))
7. Cramming More Components Onto Integrated Circuits
8. Strained Si NMOSFETs for high performance CMOS technology (2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184))
9. Electronics
10. A logic nanotechnology featuring strained-silicon (IEEE Electron Device Letters)

Their papers

• A 90-nm logic technology featuring strained-silicon (2004) — 671 citations
• Nanotechnology goals and challenges for electronic applications (2002) — 206 citations
• Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors (2000) — 188 citations
• A logic nanotechnology featuring strained-silicon (2004) — 488 citations
• A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors (2003) — 590 citations
• Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology (2004) — 160 citations
• A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply (2005) — 325 citations