Lucian Shifren
Electrical and Electronic Engineering · 2004–2016
A researcher in the Science corpus: 5 papers; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 23 citations into it
Whom Lucian Shifren trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Papers from Lucian Shifren's perspective
Ordered by how strongly the researchers Lucian Shifren trusts endorse each paper. Same corpus, a different order for every researcher.
- Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs (IEEE International Electron Devices Meeting 2003)
- Review on high-k dielectrics reliability issues (IEEE transactions on device and materials reliability)
- Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology (Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.)
- Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design (International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138))
- Cramming More Components Onto Integrated Circuits
- Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs (2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303))
- Strained Si NMOSFETs for high performance CMOS technology (2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184))
- A logic nanotechnology featuring strained-silicon (IEEE Electron Device Letters)
- A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors (IEEE International Electron Devices Meeting 2003)
- Strained silicon MOSFET technology (Digest. International Electron Devices Meeting,)
Their papers
- A 90-nm logic technology featuring strained-silicon (2004) — 671 citations
- A logic nanotechnology featuring strained-silicon (2004) — 488 citations
- A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging (2007) — 872 citations
- Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers (2006) — 138 citations
- ASAP7: A 7-nm finFET predictive process design kit (2016) — 778 citations