ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers

By Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter. International Symposium on High-Performance Computer Architecture, 2010

461 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/958dfd103c7e8c2a04d6afc2ded82760c554a879

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Citations in the corpus

Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013, background): “[4, 9, 23, 22, 32, 31]), to mitigate inter-application interference and queueing latencies in multi-core systems.”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, background): “…movement consumes a significant fraction of the total workload energy, (3) it is memory-intensive (i.e., its last-level cache misses per kilo instruction , or MPKI, is greater than 10 [21, 83, 84, 103]), and (4) data movement is the single largest component of the function’s energy consumption.”
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, methodology): “If there are multiple memory controllers, this information is sent to a centralized meta-controller at the end of a quantum, similarly to what is done in ATLAS [5].”
Memory scaling: A systems architecture perspective (2013, methodology): “To achieve these goals, we have designed various solutions including QoS-aware memory controllers [57, 58, 53, 32, 33, 54, 5, 69, 41, 23], interconnects [17, 18, 27, 28, 13, 59, 60, 19], and entire memory systems including caches, interconnect, and memory [22, 24, 19].”
The evicted-address filter: A unified mechanism to address both cache pollution and thrashing (2012, methodology): “Table 4 shows the percentage improvement of the EAF-cache over the baseline LRU policy and the best previous mechanism, SHIP, on four metrics: weighted speedup [11, 50], instruction throughput, harmonic speedup [28] and maximum slowdown [25, 26].”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “Prior works have also proposed memory scheduling algorithms (e.g., [6, 16, 23, 24, 38, 40, 41, 43]) that prioritize certain favorable requests in the memory controller to improve sys-tem performance and/or fairness.”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, unknown): “The Maximum Slowdown metric provides understanding about at most how much any of the applications in a given workload is slowed down due to sharing of memory system resources [Kim et al. 2010a].”
Efficient Coflow Scheduling Without Prior Knowledge (2015, background): “ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers.”
Reducing memory interference in multicore systems via application-aware memory channel partitioning (2011, methodology): “[11] Y. Kim et al. ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers.”
RAIDR: Retention-aware intelligent DRAM refresh (2012, methodology): “13 For these results we only evaluated the 32 workloads with 50% memory-intensive benchmarks, as this scenario of balanced memory-intensive and non-memory-intensive benchmarks is likely to be common in future systems [22].”
RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013, unknown): “Maximum Slowdown [12, 29, 30] Reduction 6% 12% 23%”
TRRespass: Exploiting the Many Sides of Target Row Refresh (2020, background): “In order to understand the modern landscape we test a set of 42 recent DDR4 modules against all standard hammering patterns: (i) single-sided, which simply activates two arbitrary (aggressor) rows in the same bank to induce bit flips in their adjacent victim rows (Figure 3a); (ii) double-sided, whic”
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, methodology): “We find that for all of our baselines and for MASK , performance with an open-row policy [71] is similar (within 0.”