Ramulator: A Fast and Extensible DRAM Simulator

By Yoongu Kim, Weikun Yang, Onur Mutlu. IEEE computer architecture letters, 2016

781 citations recorded by the source corpus.

Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as well as those of tomorrow. In this paper, we present Ramulator, a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibility. Unlike existing simulators, Ramulator is based on a generalized template for modeling a DRAM system, which is only later infused with the specific details of a DRAM standard. Thanks to such a decoupled and modular design, Ramulator is able to provide out-of-the-box support for a wide array of DRAM standards: DDR3/4, LPDDR3/4, GDDR5, WIO1/2, HBM, as well as some academic proposals (SALP, AL-DRAM, TL-DRAM, RowClone, and SARP). Importantly, Ramulator does not sacrifice simulation speed to gain extensibility: according to our evaluations, Ramulator is 2.5× faster than the next fastest simulator. Ramulator is released under the permissive BSD license.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/ff5da2bc9951173d51fcc1d50d44488702b5f1f5

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Citations in the corpus

HyGCN: A GCN Accelerator with Hybrid Architecture (2020, methodology): “This simulator models the microarchitectural behaviors of each module, which is integrated with Ramulator [34] to simulate the behaviors of memory accesses to High Bandwidth Memory (HBM).”
RowHammer: A Retrospective (2019, neutral): “In 3-D-stacked memory technologies [129], [148], e.”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, methodology): “On top of Ramulator, we build a cycle-accurate LRU cache simulator for RankCache and model of the 4-stage pipeline in the rank-NMP module.”
CACTI 7 (2017, methodology): “Memory simulators such as DRAMSim [Wang et al. 2005], USIMM [Chatterjee et al. 2012], and Ramulator [Kim et al. 2015] are performance simulators that model DRAM timing in a cycle-accurate manner.”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, methodology): “Regardless of the memory technology used to enable PIM (whether it is HMC [71], HBM [75], or some other form of 3D-stacked or compute-capable memory [85, 90, 125, 126]), any additional logic can potentially translate into a significant cost in consumer devices.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, neutral): “, Ramulator [213, 214], SoftMC [29,”
The gem5 Simulator: Version 20.0+ (2020, methodology): “Although this is not a cycle-accurate DRAM model like DRAMSim [46, 62, 73] or Ramulator [42], it is nearly as accurate while providing more flexibility and higher performance [32].”
SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning (2020, methodology): “For HBM, we simulate the number of row activation, read/write with Ramulator, and use the energy numbers from [19] to calculate overall energy.”
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator (2020, positive): “We compare DRAMsim3 with existing DRAM simulators including DRAMSim2 [14], ramulator [9], USIMM [4] and DrSim [6].”