Jingcao Hu

Computer Networks and Communications · 2003–2005

A researcher in the Science corpus: 4 papers; trusts 10 researchers and is trusted by 19 researchers here, as inferred from the citation graph.

Subfields

• Computer Networks and Communications — 20 citations into it; #1,354 of 9,886 by trust here, #3,993 by citations
• Hardware and Architecture — 18 citations into it; #297 of 1,551 by trust here, #1,043 by citations
• Electrical and Electronic Engineering — 10 citations into it; #3,272 of 16,539 by trust here, #10,714 by citations

Whom Jingcao Hu trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. William (Bill) J. Dally
2. Shashi Kumar
3. Brian Towles
4. J. L. Boudec
5. Axel Jantsch
6. Srinivasan Murali
7. Giovanni De Micheli
8. Mikael Millberg
9. Patrick Thiran
10. Luca Benini

Who trusts Jingcao Hu overall

1. Ümit Y. Ogras
2. Radu Marculescu
3. Srinivasan Murali
4. Chrysostomos Nicopoulos
5. Ming Li
6. K. Srinivasan
7. Ashutosh Kumar Singh
8. Vincenzo Catania
9. Giovanni De Micheli
10. Feihui Li

Papers from Jingcao Hu's perspective

Ordered by how strongly the researchers Jingcao Hu trusts endorse each paper. Same corpus, a different order for every researcher.

1. Networks on Chips: A New SoC Paradigm (Computer)
2. Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
3. A network on chip architecture and design methodology (Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002)
4. Network on Chip : An architecture for billion transistor era
5. Analysis of power consumption on switch fabrics in network routers (Proceedings - Design Automation Conference)
6. A generic architecture for on-chip packet-switched interconnections (Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537))
7. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (2003 Design, Automation and Test in Europe Conference and Exhibition)
8. Theory of latency-insensitive design (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.)
9. Bandwidth-constrained mapping of cores onto NoC architectures (Proceedings Design, Automation and Test in Europe Conference and Exhibition)
10. SUNMAP: a tool for automatic topology selection and generation for NoCs (Proceedings - Design Automation Conference)

Their papers

• Energy-aware mapping for tile-based NoC architectures under performance constraints (2003) — 608 citations
• DyAD - smart routing for networks-on-chip (2004) — 586 citations
• Energy- and performance-aware mapping for regular NoC architectures (2005) — 687 citations
• Key research problems in NoC design: a holistic perspective (2005) — 374 citations