Energy- and performance-aware mapping for regular NoC architectures

By Jingcao Hu, Radu Marculescu. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005

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ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006, methodology): “and the access latencies associated with global bitlines/wordlines [ 32 ].”
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, methodology): “We note that many mapping algorithms use (directly or indirectly) the average packet hop count as a cost function by relating the average number of packet hops to the communication energy consumption [70] or communication cost [115].”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, methodology): “Previous work on NoCs focused on task mapping [14], energy management [36], and reliability [21].”
Key research problems in NoC design: a holistic perspective (2005, methodology): “These techniques use the average packet hop value as a cost function by relating it to the communication energy consumption [6] or communication cost [7].”
Mapping on multi/many-core systems: Survey of current and emerging trends (2013, methodology): “In addition to communication volume as considered in [37], timing of the communication has been considered.”
"It's a small world after all": NoC performance optimization via long-range link insertion (2006, methodology): “For hotspot traffic, three arbitrarily selected nodes receive extra traffic compared with the remaining nodes, while for the MMS benchmark the traffic pattern is extracted from an A/V system [19].”