Network on Chip : An architecture for billion transistor era

By A. Hemani, Axel Jantsch, Shashi Kumar, A. Postula, Johnny Öberg, Mikael Millberg, Dan Lindqvist. 2000

491 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/262463333b60de45edc1c94e60c959fa90510c55

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Citations in the corpus

A network on chip architecture and design methodology (2002, background): “There is a general emphasis on providing efficient and standardized communication infrastructure for connecting multiple resources on the chip [11, 8, 9].”
Energy-aware mapping for tile-based NoC architectures under performance constraints (2003, background): “In [ 4 ], Hemani et al. present a honeycomb structure in which each processing core (resource) is located on a regular hexagonal node connected to three switches while these switches are directly linked to their next nearest neighbors.”
"It's a small world after all": NoC performance optimization via long-range link insertion (2006, methodology): “Therefore, it has been recently proposed to replace the custom (global) wires with structured networks-on-chips (NoCs) [4], [12], [ 18 ], [21].”
Key research problems in NoC design: a holistic perspective (2005, background): “While a handful of design problems have been recently addressed by several researchers [ 1-5 ], a formal presentation of the major research themes is still missing.”
DyAD - smart routing for networks-on-chip (2004, background): “Categories and Subject Descriptors B.4 [Hardware]: Input/output and data communications General Terms Algorithms, Performance, Design Keywords Networks-on-Chip, Systems-on-Chip, router design”
On the Design of a Photonic Network-on-Chip (2007, background): “Significant research activity has recently focused on intrachip global communication using packet-switched micronetworks [1,6,10,11,19].”
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (2008, background): “Recent research on packet-switched networks-on-chip (NoC) [9], [10], [11], [12] has shown that carefully engineered shared links can provide enough bandwidth to replace many traditional bus-based communication media and point-topoint links.”
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006, background): “As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust.”
Energy- and performance-aware mapping for regular NoC architectures (2005, background): “Digital Object Identifier 10.1109/TCAD.2005.844106 cation problems [1], [ 4 ], [5].”
QNoC: QoS architecture and design process for network on chip (2004, methodology): “We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process.”
Networks on Chip (2003, background): “[1] have proposed a packet switched architecture with switches surrounded by six resources and connected to 6 neighboring switches.”