K. Srinivasan

Computer Networks and Communications · with Chatha · 2006

A researcher in the Science corpus: 1 paper; trusts 4 researchers and is trusted by 2 researchers here, as inferred from the citation graph.

Subfields

• Computer Networks and Communications — 11 citations into it; #6,298 of 9,886 by trust here, #8,543 by citations
• Hardware and Architecture — 10 citations into it; #899 of 1,551 by trust here, #1,384 by citations
• Electrical and Electronic Engineering — 5 citations into it; #8,915 of 16,539 by trust here, #14,827 by citations

Whom K. Srinivasan trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. William (Bill) J. Dally
2. Jingcao Hu
3. Tang Lei
4. Shashi Kumar
5. Brian Towles
6. Radu Marculescu
7. David S. Johnson
8. Luca Benini
9. Mikael Millberg

Who trusts K. Srinivasan overall

1. Ümit Y. Ogras
2. Radu Marculescu

Papers from K. Srinivasan's perspective

Ordered by how strongly the researchers K. Srinivasan trusts endorse each paper. Same corpus, a different order for every researcher.

1. A network on chip architecture and design methodology (Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002)
2. Route packets, not wires: on-chip interconnection networks (Proceedings - Design Automation Conference)
3. Networks on Chips: A New SoC Paradigm (Computer)
4. Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (2003 Design, Automation and Test in Europe Conference and Exhibition)
5. The future of wires (Proceedings of the IEEE)
6. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip (Proceedings Design, Automation and Test in Europe Conference and Exhibition)
7. Orion: a power-performance simulator for interconnection networks (35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings.)
8. Energy-aware mapping for tile-based NoC architectures under performance constraints (Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.)
9. The NP-Completeness Column: An Ongoing Guide
10. The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs (IEEE Micro)

Their papers

• Linear programming based techniques for synthesis of network-on-chip architectures (2006) — 306 citations