A generic architecture for on-chip packet-switched interconnections

By P. Guerrier, A. Greiner. Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537), 2000

1,012 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/509a1d6c68644794b69ae3a8d16207389c4733b8

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Hardware and Architecture

Citations in the corpus

Energy-aware mapping for tile-based NoC architectures under performance constraints (2003, background): “These IPs can be CPU or DSP cores, video stream processors, high-bandwidth I/O, etc[ 1 ].”
Networks on chip: a new paradigm for systems on chip design (2002, background): “Techniques such as bus encoding [5] and packetization [4, 11] have been proposed, but much research has still to be carried out to determine which networking techniques are most appropriate for SoCs and which parameters fit best this new context.”
QNoC: QoS architecture and design process for network on chip (2004, methodology): “We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process.”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, methodology): “Both BFT and fat tree (SPIN) networks show a very large reduction in energy when 3D ICs are used.”
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006, background): “As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust.”
SUNMAP: a tool for automatic topology selection and generation for NoCs (2004, methodology): “The need to replace busses with on-chip networks has been presented in [1, 2]. Several NoC architectures and design methodologies have been presented recently, such as mesh based Nostrum [4] and aSoC [8], fat-tree based SPIN [ 3 ], ring based Proteo [9], etc.”
Performance evaluation and design trade-offs for network-on-chip interconnect architectures (2005, background): “Guerrier and Greiner [17] have proposed a generic interconnect template called SPIN (Scalable, Programmable , Integrated Network) for on-chip packet switched interconnections, where a fat-tree architecture is used to interconnect IP blocks.”
HERMES: an infrastructure for low area overhead packet-switching networks on chip (2004, methodology): “SPIN - 2000 [8] [16] [17] Fat -tree / deterministic and adaptive 32 bits data + 4 bits control Input queue + 2 shared output queue VCI 0.”
Xpipes: a network-on-chip architecture for gigascale systems-on-chip (2004, background): “Several researchers [5, 6, 7, 8] envision NoCs as regular tile-based topologies (such as mesh networks and fat trees), which are suitable for interconnecting homogeneous cores in a chip multiprocessor.”
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure (2006, methodology): “We distinguish two networks: The downward network inspired from SPIN [6], based on the Butter.y Fat-Tree(BFT) style interconnect [9] with linear populated and unidirectional switch boxes.”
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (2003, background): “Networks on a chip(NoC) are emerging as an alternative to existing on-chip interconnects because they (a) structure and manage global wires in new deep-submicron technologies [2–5,7], (b) share wires, lowering their number and increasing their utilization [5,7], (c) can be energy efficient and relia”
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005, background): “The Scalable Programmable Integrated Network (SPIN) described in [3] is another regular, fat-tree-based network architecture.”