A network on chip architecture and design methodology

By Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, M. Forsell, Kari Tiensyrjä, A. Hemani. Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, 2002

1,367 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/5c74cae679df7abf4bd5b45f32a341eb5705c6b8

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Citations in the corpus

Networks on Chip (2003, methodology): “[6] put forward a detailed packet switched, mesh based on-chip communication infra-structure together with a design methodology.”
Xpipes: a network-on-chip architecture for gigascale systems-on-chip (2004, background): “Several researchers [5, 6, 7, 8] envision NoCs as regular tile-based topologies (such as mesh networks and fat trees), which are suitable for interconnecting homogeneous cores in a chip multiprocessor.”
HERMES: an infrastructure for low area overhead packet-switching networks on chip (2004, methodology): “Nostrum—2001 [5,6] 2D mesh (scalable)/hot”
DyAD - smart routing for networks-on-chip (2004, methodology): “The regular tile-based NoC architecture was recently proposed as a solution to the complex on-chip communication problems [3][6][ 8 ].”
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip (2004, background): “This has led to proposals for building regular packet switched networks on chip as suggested by Dally, Sgroi, and Kumar [6, 7, 8 ]. These Network-on-Chips (NoCs) are the network based communication solution for SoCs.”
Energy- and performance-aware mapping for regular NoC architectures (2005, methodology): “To solve this issue, region-based NoC allows the regular NoC designs to embed irregular regions [5].”
Linear programming based techniques for synthesis of network-on-chip architectures (2006, background): “[20] were early works that motivated the design of NoC for supporting on-chip communication.”
A two-step genetic algorithm for mapping task graphs to a network on chip architecture (2003, methodology): “In the NoC paradigm a router-based network is used for packet switched on-chip communication among cores [4,5,6].”
Bandwidth-constrained mapping of cores onto NoC architectures (2004, methodology): “To overcome this problem, Networks on Chips (NoCs) have been proposed and used for interconnecting the cores [2, 3, 4] and replacing dumb physical routing.”
QNoC: QoS architecture and design process for network on chip (2004, methodology): “We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process.”
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005, methodology): “The NOSTRUM network described in [5] takes this approach: The platform includes both a mesh topology and the relative design methodology, wherein a concrete architecture is derived from a general NoC template, then application mapping follows.”
Performance evaluation and design trade-offs for network-on-chip interconnect architectures (2005, methodology): “[18] have proposed a mesh-based interconnect architecture called CLICH E (Chip-Level Integration of Communicating Heterogeneous Elements).”
3-D Topologies for Networks-on-Chip (2006, background): “The gate leakage component is due to current flowing through the gate oxide, denoted as .”