Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip

By E. Rijpkema, Kees G. W. Goossens, A. Radulescu, J. Dielissen, J. V. Meerbergen, P. Wielage, Erwin Waterlander. 2003 Design, Automation and Test in Europe Conference and Exhibition, 2003

522 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/667a4d9d61ecd06fe5dea9acc2f10142b578b4d8

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Citations in the corpus

Linear programming based techniques for synthesis of network-on-chip architectures (2006, background): “The existing work on NoC design has chiefly concentrated on performance evaluation [4] [6] [7], router architecture design [8] [9], designer specified network instantiation [10], and error control [11] [12].”
SUNMAP: a tool for automatic topology selection and generation for NoCs (2004, background): “In [5], designing NoC with Quality-of-Service (QoS) guarantees has been explored.”
HERMES: an infrastructure for low area overhead packet-switching networks on chip (2004, background): “As described in [9][10], NoCs are emerging as a possible solution to the existing interconnection architecture constraints, due to the following characteristics: (i) energy efficiency and reliability [6]; (ii) scalability of bandwidth when compared to traditional bus architectures; (iii) reusability”
A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip (2005, methodology): “A similar approach is seen in the ÆTHEREAL router [16].”
DyAD - smart routing for networks-on-chip (2004, background): “In deterministic routing (also called oblivious routing), the path is completely determined by the source and the destination address.”
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005, methodology): “The Aethereal NoC design framework presented in [7] aims at providing a complete infrastructure for developing heterogeneous NoC with end-to-end quality of service guarantees.”
Bandwidth-constrained mapping of cores onto NoC architectures (2004, unknown): “2 Previous Works We refer the reader to several recent surveys [2, 3, 4, 5] on NoCs for pointers to recent research and development.”
Xpipes: a network-on-chip architecture for gigascale systems-on-chip (2004, methodology): “The Aethereal NoC design framework presented in [30] aims at providing a complete infrastructure for developing heterogeneous NoCs with end-to-end quality of service guarantees.”
Analysis of error recovery schemes for networks on chips (2005, background): “Industry and academia recognize the interconnect problem as one of the important d esign constraints, and consequently, packetbased on chip communication networks (known as Network on Chips (NoCs) ) have been proposed to address the challenges of increasing interconnect complex ity [3], [8], [10], [”