Networks on Chips: A New SoC Paradigm

By Luca Benini, Giovanni De Micheli. Computer, 2002

4,067 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/20d549d3180fb26fdc21c65874b982274ca053af

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Citations in the corpus

Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems (2011, background): “THE Network-on-Chip (NoC) paradigm has emerged as a communication backbone to enable a high degree of integration in multicore System-on-Chips (SoCs) [1].”
Research Challenges for On-Chip Interconnection Networks (2007, background): “SoC architectures in which a large number of diverse IP blocks is the rule rather than the exception exacerbate these needs.(14) Supporting multiple cores on a single chip also reveals new management problems.”
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006, background): “As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust.”
Key research problems in NoC design: a holistic perspective (2005, background): “While a handful of design problems have been recently addressed by several researchers [1-5], a formal presentation of the major research themes is still missing.”
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (2011, background): “Networks-on-Chip (NoC) [7], provide bandwidth scalability, but the latency of traditional NoCs is not adequate for L1 processor-to-memory communication [8], and highly optimized special-purpose interconnects are required.”
SUNMAP: a tool for automatic topology selection and generation for NoCs (2004, methodology): “The need to replace busses with on-chip networks has been presented in [1, 2 ]. Several NoC architectures and design methodologies have been presented recently, such as mesh based Nostrum [4] and aSoC [8], fat-tree based SPIN [3], ring based Proteo [9], etc.”
HERMES: an infrastructure for low area overhead packet-switching networks on chip (2004, methodology): “As mentioned in [5,8], when applied to NoCs the lower three layers (physical, link, and network) are technology dependent.”
Linear programming based techniques for synthesis of network-on-chip architectures (2006, background): “Network-on-Chip(NoC) hasbeenproposedasa solution for the communicationchallengesin the nanoscaleregime [1] [2].”
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip (2004, methodology): “Multi-cast can easily be implemented by having multiple destinations along the VC path, as illustrated by VCB of Figure 7, which has destinations in [1,1] and [2, 3 ] .E ven several source/destination pairs can be formed along a VC path subscribed to the same TDN as long as they are aligned so that ”
A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip (2005, background): “There is a general consensus that shared, segmented interconnection networks, so called networks-on-chip (NoC), constitute a viable solution space to the problems faced today [4][7][10].”
3-D Topologies for Networks-on-Chip (2006, methodology): “This effective capacitance is determined from the methodology described in [30], [31].”
DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip (2006, methodology): “Here, we use an uniform network communication pattern to model the traffic load of where Ai can be calculated using Equations (1), (2), and each router with both static XY and DyXY routing algo- (3).”
"It's a small world after all": NoC performance optimization via long-range link insertion (2006, background): “The need for scalable communication architectures is discussed in [4], [12], [18], [21], and [36], while several concrete NoC architectures are presented in [1], [3], [5], [6], [17], [24], and [26].”
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS (2008, background): “THE scaling of MOS transistors into the nanometer regime opens the possibility for creating large scalable Network-on-Chip (NoC) architectures [1] containing hundreds of integrated processing elements with on-chip communica-”