Route packets, not wires: on-chip interconnection networks

By William (Bill) J. Dally, Brian Towles. Proceedings - Design Automation Conference, 2001

3,697 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/5bc8c69d6605afa5e2524a3a0c4deca750d60ba8

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Citations in the corpus

DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip (2006, background): “A layered architecture called Network on Chip (NoC) [1] [2] has been proposed for global communication in complex SoCs to meet the performance requirements.”
HERMES: an infrastructure for low area overhead packet-switching networks on chip (2004, background): “20 bits at each 200MHz clock cycle [20]).”
Energy- and performance-aware mapping for regular NoC architectures (2005, methodology): “In [1], Dally et al. suggest using the on-chip interconnection networks instead of ad hoc global wiring to structure the toplevel wires on a chip and facilitate truly modular design.”
Flattened Butterfly Topology for On-Chip Networks (2007, methodology): “Most on-chip networks that have been proposed are lowradix, mostly utilizing a 2D mesh or a torus network [10].”
A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip (2005, background): “There is a general consensus that shared, segmented interconnection networks, so called networks-on-chip (NoC), constitute a viable solution space to the problems faced today [4][ 7 ][10].”
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, methodology): “3) Proposed Approaches: Seminal work on router power modeling [131] along with position papers that highlight the importance of NoC power consumption [15], [40], [74] motivates research into low-power NoCs.”
Power reduction techniques for microprocessor systems (2005, background): “Several authors [Zhang et al. 2001; Dally and Towles 2001; Sgroi et al. 2001] propose the application of these techniques at the chip level.”
A network on chip architecture and design methodology (2002, background): “It has also been realized that the key to reuse and integration of IP components is the communication from the physical to the system and conceptual level, and consequently communication centric architectures, platforms and methodologies have been developed [8, 9, 10].”
On the Design of a Photonic Network-on-Chip (2007, background): “Significant research activity has recently focused on intrachip global communication using packet-switched micronetworks [1,6,10,11,19].”
Networks on chip: a new paradigm for systems on chip design (2002, background): “We refer the interested reader to an extended overview of this problem [1] and to some recent results in this area in industry [21, 10] and academia [4, 5].”
DyAD - smart routing for networks-on-chip (2004, background): “The regular tile-based NoC architecture was recently proposed as a solution to the complex on-chip communication problems [3].”
QNoC: QoS architecture and design process for network on chip (2004, methodology): “We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process.”
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006, background): “As diminishing feature sizes have led to increases in global wiring delays, Network-on-Chip (NoC) architectures are viewed as a possible solution to the wiring challenge and have recently crystallized into a significant research thrust.”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, background): “The two dominant interconnects in the SoC research community have been buses and Networks-on-Chip (NoC) [8, 3].”