James E. Smith

Hardware and Architecture · Computer · 1984–2014

A researcher in the Science corpus: 7 papers; trusts 7 researchers and is trusted by 18 researchers here, as inferred from the citation graph.

Subfields

Hardware and Architecture — 12 citations into it; #132 of 1,551 by trust here, #370 by citations
Computer Networks and Communications — 8 citations into it; #2,798 of 9,886 by trust here, #3,005 by citations

Their strongest outbound trust, strongest first, inferred from their citations.

Ordered by how strongly the researchers James E. Smith trusts endorse each paper. Same corpus, a different order for every researcher.

Reconfigurable caches and their application to media processing (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures (Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000)
An Adaptive Issue Queue for Reduced Power at High Performance
POWER4 system microarchitecture (IBM Journal of Research and Development)
Balancing thoughput and fairness in SMT processors (2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.)
Dynamo: a transparent dynamic optimization system (ACM-SIGPLAN Symposium on Programming Language Design and Implementation)
Fair cache sharing and partitioning in a chip multiprocessor architecture (Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.)
Dead-block prediction & dead-block correlating prefetchers (Proceedings 28th Annual International Symposium on Computer Architecture)
Memory access scheduling (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
Reducing power density through activity migration (Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03.)