POWER4 system microarchitecture

By Joel M. Tendler, J. S. Dodson, J. S. Fields, Hung Q. Le, B. Sinharoy. IBM Journal of Research and Development, 2002

671 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/99d4c73c44f1049bf1e31f4f11f561d67eb5524d

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Onur Mutlu
2. Jichuan Chang
3. G. Sohi
4. David A. Wood
5. Bradford M. Beckmann
6. Moinuddin K. Qureshi
7. Yale N. Patt
8. Krste Asanovic

In Hardware and Architecture

1. Onur Mutlu
2. Jichuan Chang
3. G. Sohi
4. David A. Wood
5. Margaret Martonosi
6. Canturk Isci
7. Bradford M. Beckmann
8. Yale N. Patt

Citations in the corpus

• Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors (2005, methodology): “Existing CMP designs [4, 17, 18, 25] adopt a “dancehall” configura-tion, where processors with private primary caches are on one side of an interconnect crossbar and a shared L2 cache is on the other.”
• Adaptive cache compression for high-performance processors (2004, background): “, separate L1 instruction and data caches and a unified L2 cache), with some recent architectures having threelevel cache hierarchies [39].”
• An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (2006, background): “Initially, this era of chip multiprocessing (CMP) [35, 40] began with a stepback in core-level frequency (shallower processor pipelines) to allow multi-core (multi-thread) throughput increase at affordable power [15, 16, 18, 29, 41].”
• Detailed design and evaluation of redundant multi-threading alternatives (2002, methodology): “We also describe and analyze a simple extension to the proposed SRT design, called preferential space redundancy, which significantly improves coverage of permanent faults.”
• Cooperative Caching for Chip Multiprocessors (2006, background): “2For example, IBM Power4 systems [ 32 ] add two states (SL and T) to their MESI-based coherence protocol to partially support cache-to-cache transfers of clean data, but don’t select follow-up owners when the initial owner replaces the block.”
• Data Cache Prefetching Using a Global History Buffer (2004, background): “Early sequential methods always prefetch after each cache miss [13], while more recent sequential methods [15] wait to issue prefetches until a sequential access pattern is detected.”
• A NUCA Substrate for Flexible CMP Cache Sharing (2007, methodology): “For instance, the dual-processor Power4 CMP [23] uses three banks, and the eight-processor Piranha CMP uses eight banks for each L2 cache.”
• Managing Wire Delay in Large Chip-Multiprocessor Caches (2004, methodology): “We base our prefetching strategy on the IBM Power 4 implementation [43] with some slight modifications.”
• POWER5 system microarchitecture (2005, methodology): “Introduction IBM introduced the POWER4* systems in 2001 [1].”
• IBM Power5 chip: a dual-core multithreaded processor (2004, background): “40 IBM introduced Power4-based systems in 2001.(1) The Power4 design integrates two processor cores on a single chip, a shared second-level cache, a directory for an off-chip third-level cache, and the necessary circuitry to connect it to other Power4 chips to form a system.”
• Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, neutral): “In this paper, we assume that the last-level (L2) cache and off-chip DRAM bandwidth are shared by multiple cores on a chip as in many commercial CMPs [1, 11, 29, 31].”
• Microarchitectural techniques for power gating of execution units (2004, methodology): “The modeled microarchitecture is similar to a current generation POWER4 like microprocessor [16].”
• Accelerating critical section execution with asymmetric multi-core architectures (2009, background): “.nd that, on average, ACS reduces the number of L2 cache misses inside the critical sections by 20%.2 On the other hand, executing critical sections exclusively on a large core of an ACMP can have a negative effect.”
• Token Coherence: decoupling performance and correctness (2003, background): “Power4 [42] and xSeries Summit [10] systems).”