An Adaptive Issue Queue for Reduced Power at High Performance

By Alper Buyuktosunoglu, S. Schuster, David M. Brooks, Pradip Bose, P. Cook, D. Albonesi. 2000

116 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. James E. Smith
2. Ashutosh S. Dhodapkar
3. Pradip Bose
4. Kevin Skadron
5. Mircea R. Stan
6. David M. Brooks
7. Karthik Sankaranarayanan
8. Alper Buyuktosunoglu

In Hardware and Architecture

1. Karthik Sankaranarayanan
2. Kevin Skadron
3. Mircea R. Stan
4. James E. Smith
5. Ashutosh S. Dhodapkar
6. Pradip Bose
7. David M. Brooks
8. Alper Buyuktosunoglu

In ML Systems & Hardware

1. James E. Smith
2. David M. Brooks

Citations in the corpus

• HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects (2003, background): “Recently, a great deal of research work in the architecture community has focused o n r ucing leakage power in the caches [11, 13, 14, 18, 22, 27, 28], branch predictor [15, 16], regi ster file [2], issue queues [12, 21, 8, 9], and the ALUs [10].”
• Managing multi-configuration hardware via dynamic working set analysis (2002, methodology): “One promising optimization method is to configure microarchitecture features dynamically to adapt to changing program characteristics [1-13].”
• Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors (2000, background): “Brooks et al., 4 for example, provides categories of structures modeled for power: 1) array structures including caches, register files, and branch prediction tables; 2) content-addressable memory (CAM) structures including those used in issue queue logic, translation look-aside buffers (TLBs); 3)…”