Data Cache Prefetching Using a Global History Buffer

By Kyle J. Nesbit, James E. Smith. International Symposium on High-Performance Computer Architecture, 2004

417 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/3933d3380710680865441c87a22d691ba751a2ef

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Onur Mutlu
2. Mahmut Taylan Kandemir
3. Adwait Jog
4. R. Iyer
5. Thomas F. Wenisch
6. Asit K. Mishra
7. Onur Kayiran
8. Nachiappan Chidambaram Nachiappan

In Hardware and Architecture

1. Mahmut Taylan Kandemir
2. Onur Mutlu
3. Adwait Jog
4. R. Iyer
5. Asit K. Mishra
6. Onur Kayiran
7. Nachiappan Chidambaram Nachiappan
8. Chita R. Das

Citations in the corpus

• Spatial Memory Streaming (2006, background): “We consider GHB with two history buffer sizes: 256 entries (sufficient for SPEC applications [12,20]) and 16k entries (to roughly match the capacity of the SMS PHT).”
• OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013, background): “, [13, 23, 45, 52]) have been proposed within the context of CPU systems.”