Reducing power density through activity migration
By Seongmoo Heo, Kenneth C. Barr, Krste Asanovic. Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03., 2003
342 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/7d09f096396c7c24ffa6e72e00740c3855623f35
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Electrical and Electronic Engineering
- Margaret Martonosi
- Kevin Skadron
- Mircea R. Stan
- Karthik Sankaranarayanan
- James Mc Donald
- Sivakumar Velusamy
- Wei Huang
- David M. Brooks
Citations in the corpus
- Temperature and supply Voltage aware performance and power modeling at microarchitecture level (2005, methodology): “However, no coupled power and thermal management is studied in [20].”
- Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction (2003, methodology): “Recently, it has also been used for reducing power density [19] in a homogeneous multiplecore architecture, through the use of frequent core switches to idle processors.”
- The case for lifetime reliability-aware microprocessors (2004, methodology): “We also model the impact of temperature on leakage power using the technique in [9].”
- Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, background): “[9] and Stavrou and Trancoso [34] minimize power density or temperature hot spots by judiciously scheduling jobs or migrating them from core to core.”
- The impact of technology scaling on lifetime reliability (2004, methodology): “We also model the impact of temperature on leakage power using the technique described in [7].”
- Thread motion: fine-grained power management for multi-core systems (2009, background): “[8] argue that the interval between core migrations can be smaller than typical OS context swap times for maximum benefit.”
- Heat-and-run: leveraging SMT and CMP to manage power density through the operating system (2004, methodology): “However, this competition can cause execution resources such as ALUs to heat quickly.”
- Temperature-aware microarchitecture: Modeling and implementation (2004, result): “But these results and recent work by Heo et al. [2003] suggest the potential of trading-off area for thermal control.”
- An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (2006, background): “Prior research in this area has been primarily limited to studying the efficacy of providing dynamic management of power and thermal hot spots through localized responses provided at the core-level [2, 11] or through global scheduling heuristics [7, 22, 37].”
- Techniques for Multicore Thermal Management: Classification and New Exploration (2006, methodology): “For calculating leakage dynamically, we use the temperatures reported by HotSpot as input to a leakage model based on an empirical equation from [17].”