Reconfigurable caches and their application to media processing

By Parthasarathy Ranganathan, Sarita V. Adve, N. Jouppi. Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000

300 citations recorded by the source corpus.

High performance general-purpose processors are increasingly being used for a variety of application domains-scientific, engineering, databases, and more recently, media processing. It is therefore important to ensure that architectural features that use a significant fraction of the on-chip transistors are applicable across these different domains. For example, current processor designs often devote the largest fraction of on-chip transistors (up to 80%) to caches. Many workloads, however, do not make effective use of large caches; e,g., media processing workloads which often have streaming data access patterns and large working sets. This paper proposes a new reconfigurable cache design. This design enables the cache SRAM arrays to be dynamically divided into multiple partitions that can be used for different processor activities. These activities can benefit applications that would otherwise not use the storage allocated to large conventional caches. Our design involves relatively few modifications to conventional cache design, and analysis using a modification of the CACTI analytical model shows a small impact on cache access time. We evaluate one representative use of reconfigurable caches-instruction reuse for media processing. We find this use gives IPC improvements ranging from 1.04X to 1.20X in simulation across eight media processing benchmarks.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/d414e0a7c7d223f278fcff3055888871a3ddcf9f

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In Electrical and Electronic Engineering

In Hardware and Architecture

Citations in the corpus

Heracles: Improving resource efficiency at scale (2015, background): “Isolation mechanisms: There is significant work on shared cache isolation, including soft partitioning based on replacement policies [77, 78], way-partitioning [65, 64], and finegrained partitioning [68, 49, 71].”
Fair cache sharing and partitioning in a chip multiprocessor architecture (2004, methodology): “The first approach relies on modifying the cache placement algorithm by restricting where data can be placed in the cache [14, 10].”
Managing multi-configuration hardware via dynamic working set analysis (2002, methodology): “One promising optimization method is to configure microarchitecture features dynamically to adapt to changing program characteristics [1-13].”
Phase tracking and prediction (2003, background): “Another form of re-configurable cache that has been proposed dynamically divides the data cache into multiple partitions, each of which can be used for a different function such as instruction reuse buffers, value predictors, etc [18].”
A highly configurable cache architecture for embedded systems (2003, background): “Ranganathan [22] proposed a configurable cache architecture for a generalpurpose microprocessor.”
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures (2000, methodology): “Key to our approach is the exploitation of the properties of conventional caches and future technology trends in order to provide cache and TLB con.gurability in a low-intrusive manner.”