Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures

By Rajeev Balasubramonian, D. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas. Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000, 2000

397 citations recorded by the source corpus.

Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that leverages repeater insertion to provide dynamic low-cost configurability trading off size and speed on a per application phase basis. A novel configuration management algorithm dynamically detects phase changes and reacts to an application's hit and miss intolerance in order to improve memory hierarchy performance while taking energy consumption into consideration. When applied to a two-level cache and TLB hierarchy at 0.1 /spl mu/m technology, the result is an average 15% reduction in cycles per instruction (CPI), corresponding to an average 27% reduction in memory-CPI, across a broad class of applications compared to the best conventional two-level hierarchy of comparable size. Projecting to sub-.1 /spl mu/m technology design considerations that call for a three-level conventional cache hierarchy for performance reasons, we demonstrate that a configurable L2/L3 cache hierarchy coupled with a conventional LI results in an average 43% reduction in memory hierarchy energy in addition to improved performance.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/f77a12ca006add3b760c796440b309c6f3388ad7

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Citations in the corpus

SimPoint 3.0: Faster and More Flexible Program Phase Analysis (2005, methodology): “Balasubramonian et al. [8] proposed using hardware counters to collect miss rates, CPI and branch frequency information for every 100,000 instructions.”
A highly configurable cache architecture for embedded systems (2003, background): “[3] R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas, Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures, Int.”
Phase tracking and prediction (2003, neutral): “In [2], Balasubramonian et.”
Managing multi-configuration hardware via dynamic working set analysis (2002, methodology): “One promising optimization method is to configure microarchitecture features dynamically to adapt to changing program characteristics [ 1-13 ].”
Runtime power monitoring in high-end processors: methodology and empirical data (2003, methodology): “Several prior papers have proposed methods for detecting or exploiting program phases[1, 5, 9, 22, 23, 29].”
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors (2000, methodology): “Albonesi et al.(1,2) in the CAP (Complexity-Adaptive Processors) project at the University of Rochester, have studied the power and performance advantages in dynamically adapting on-chip resources in tune with changing workload characteristics.”