Addressing the system-on-a-chip interconnect woes through communication-based design

By M. Sgroi, M. Sheets, A. Mihal, Kurt Keutzer, Sharad Malik, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli. Proceedings - Design Automation Conference, 2001

403 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b9b0cbfc18ae34ce640d7c093301a750d4436311

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Citations in the corpus

Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip (2004, neutral): “[8] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Öberg, K.Tiensyrjä, and A. Hemani, A Network-on-Chip Architecture and Design Methodology.”
Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design (2007, methodology): “This is a significant deviation from the work on high-level synthesis pioneered by the CMU school [67] where from a high-level design representation, both architecture and micro-architecture implementations were automatically generated.”
Orion: a power-performance simulator for interconnection networks (2002, background): “Single-chip multiprocessor systems are seeing the use of interconnection networks as the only scalable solution to inter-processor communication [16].”
Networks on Chip (2003, background): “[5] provide general discussions and motivations for communication centric on-chip architectures and platforms and for the strict conceptual separation of computation from communication.”
Power reduction techniques for microprocessor systems (2005, background): “Several authors [Zhang et al. 2001; Dally and Towles 2001; Sgroi et al. 2001] propose the application of these techniques at the chip level.”
"It's a small world after all": NoC performance optimization via long-range link insertion (2006, background): “The need for scalable communication architectures is discussed in [4], [12], [18], [21], and [36], while several concrete NoC architectures are presented in [1], [3], [5], [6], [17], [24], and [26].”
HERMES: an infrastructure for low area overhead packet-switching networks on chip (2004, methodology): “The two most prominent interface standards, VCI and OCP are each used by two of the NoC proposals presented in Table 1. The Proteo [25][26][27] and SPIN [16][17] NoCs declare to use VCI, while Sgroi [ 20 ] and Hermes [28] employ OCP.”
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005, neutral): “Since port[1] of SW_0 has only a”
A network on chip architecture and design methodology (2002, background): “It has also been realized that the key to reuse and integration of IP components is the communication from the physical to the system and conceptual level, and consequently communication centric architectures, platforms and methodologies have been developed [8, 9, 10].”
Methods for evaluating and covering the design space during early design development (2004, methodology): “Knowledge from interface synthesis [118–121] can be reused for the hardware part of a wrapper, whereas following the approach of Networks-on-Chip [117] based on standard network interfaces affects protocol stacks on programmable cores.”
QNoC: QoS architecture and design process for network on chip (2004, methodology): “We define Quality of Service (QoS) and cost model for communications in Systems on Chip (SoC), and derive related Network on Chip (NoC) architecture and design process.”
SUNMAP: a tool for automatic topology selection and generation for NoCs (2004, methodology): “This motivates a shift in the communication design paradigm from non-scalable bus based architectures to scalable Networks on Chip (NoC) based architectures [1, 2, 3, 4].”
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip (2003, methodology): “A key ingredient in tackling this challenge is decoupling the computation from communication[10, 14 ].”