Ultrathin high-K gate stacks for advanced CMOS devices

By Evgeni P. Gusev, D. Buchanan, Eduard A. Cartier, A. Kumar, D. DiMaria, Supratik Guha, A. Callegari, Sufi Zafar, P. Jamison, D. Neumayer and 13 more. International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001

224 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/a26687a35bea6da97be11db87eb3b96d465b25dd

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In Electrical and Electronic Engineering

Citations in the corpus

Threshold Voltage Instabilities in High- Gate Dielectric Stacks (2005, methodology): “As shown in the previous sections, many high- gate dielectrics exhibit excessive charge trapping as compared to scaled SiO or oxinitride (SiON) layers, and threshold voltage instabilities remain a major concern for the implementation of high- materials into the gate stack of future CMOS technologies”
Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation (2010, background): “It has been shown that both these obstacles can be resolved by replacing the polysilicongate electrode by a metal electrode [5], [6].”
Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics (2004, background): “From the difference between the conventional split-C–V and the Hall-effect data, one can calculate the trap density, which in this case amounts to slightly over 1 cm , and this number is in good agreement with the trap density extracted from the subthreshold slope and charge trapping measurement [3]”
High- /Metal-Gate Stack and Its MOSFET Characteristics (2004, background): “It has also been reported that high- /poly-Si transistors exhibit severely degraded channel mobility [ 12 ], [13].”
Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics (2003, background): “challenge for their use in future CMOS technologies [4], [5].”
Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks (2005, methodology): “High- films were deposited by atomic layer deposition (ALD) on p-type silicon substrate with doping density cm ; details of device fabrications are given elsewhere [6], [58].”
Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics (2003, methodology): “It has been widely reported for CMOS fabricated on (100) substrates that carrier mobility is lower in CMOS with highdielectrics compared with conventional oxide or oxynitride, possibly due to fixed charge, charge trapping, and remote phonon scattering [2].”
Fermi-level pinning at the polysilicon/metal-oxide interface-Part II (2004, background): “There is widespread data in the literature suggesting that pMOS devices with Hf-based dielectrics have higher poly-Si depletion than their respective oxide controls [1], [2], [ 4 ], [8], [11].”
High-/spl kappa//metal-gate stack and its MOSFET characteristics (2004, background): “It has been reported that Fermi-level pinning at the high- /poly-Si transistors causes high threshold voltages in MOSFET transistors [9], resulting in poor transistor drive performance.”
Nanotechnology goals and challenges for electronic applications (2002, background): “Gate oxide leakage is increasing exponentially with each new generation due to oxide thickness scaling and is beginning to approach transistor subthreshold leakage values ( 1 nA/ m). To address this limitation, a significant amount of research is underway on high- gate dielectrics to replace SiO [ 2”