Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

By C. Hobbs, L. Fonseca, A. Knizhnik, V. Dhandapani, S. Samavedam, W. Taylor, J. Grant, L. Dip, D. Triyoso, R. Hegde and 10 more. IEEE Transactions on Electron Devices, 2004

171 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/9588219a81494a96a431c5abad637578972aff09

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In Electrical and Electronic Engineering

1. Ya. I. Alivov
2. Kaustav Banerjee
3. Hadis Morkoç
4. Natalia Izyumskaya
5. Hong Li
6. Navin Srivastava
7. Chuan Xu

Citations in the corpus

• Oxides, Oxides, and More Oxides: High-κ Oxides, Ferroelectrics, Ferromagnetics, and Multiferroics (2009, background): “170 , 171 explained the shift by the Fermi-level pinning at the interface, which in turn was attributed interfacial Si–Hf and Si–O–Al bonds for HfO 2 and Al 2 O 3 , respectively.”
• Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation (2010, background): “Fermi level pinning [3] occurs due to high density of the defects formed at the polysilicon/high-k dielectric interface, which results in shifting of the threshold voltage (Vth) to higher values, thereby lowering the device drive current.”