Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics
By Andreas Kerber, Eduard A. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. Maes, U. Schwalke. IEEE Electron Device Letters, 2003
349 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/a80cca2fbbf25574f94b305d809b239068f0dc8b
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In Electrical and Electronic Engineering
- Eduard A. Cartier
- Evgeni P. Gusev
- Arvind Kumar
- Sufi Zafar
- Andreas Kerber
- John Robertson
- Dieter K. Schroder
Citations in the corpus
- Threshold Voltage Instabilities in High- Gate Dielectric Stacks (2005, background): “This paper summarizes our recent work on threshold voltage instability due to charge trapping [6], [41], [43], [44], negative bias temperature instability (NBTI) [53], [54], hot-carrier stressing [46], [47], de-trapping kinetics [41], [55] and transient charge trapping effects [ 38 ]‐[40], [51] in h”
- Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks (2005, background): “Finally, results obtained by the transient methods listed above will be compared and a simple defect model [38] to explain the transient phenomena will be discussed.”
- Review on high-k dielectrics reliability issues (2005, background): “To take into account this polarity and time dependence, a team [16] has”
- Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks (2009, methodology): “Electron trapping has been attributed to defects in the IL (oxygen deficiency-related defect precursors) [22], defects at the interface between the two dielectrics [21], defects in the HfO2 layer [ 23 ], and defects at”