IBM Power5 chip: a dual-core multithreaded processor

By R. Kalla, B. Sinharoy, Joel M. Tendler. IEEE Micro, 2004

417 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

A NUCA Substrate for Flexible CMP Cache Sharing (2007, methodology): “based protocols can reduce the area overhead for sharing vectors [11, 23], we used the directory protocol because it is more scalable for these types of systems, demanding less L2-to-L1 bandwidth than broadcast protocols.”
Managing Wire Delay in Large Chip-Multiprocessor Caches (2004, neutral): “Small-scale chip multiprocessors cially available [24, 30, 44].”
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (2006, methodology): “Initially, this era of chip multiprocessing (CMP) [35, 40] began with a stepback in core-level frequency (shallower processor pipelines) to allow multi-core (multi-thread) throughput increase at affordable power [15, 16, 18, 29, 41].”
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors (2008, background): “At the chip scale, the trend toward multicore architectures and chip multiprocessors (CMPs) for driving performance-per-watt by increasing the number of parallel computational cores is dominating new commercial releases [2], [3], [4], [5], [6].”