Adaptive cache compression for high-performance processors
By Alaa R. Alameldeen, David A. Wood. Proceedings. 31st Annual International Symposium on Computer Architecture, 2004., 2004
326 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/87fcebc1fea96be854a93663722f08b33e80a167
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Onur Mutlu
- Vivek Seshadri
- Michael A. Kozuch
- Todd C. Mowry
- Phillip B. Gibbons
- Christos Kozyrakis
- Gennady Pekhimenko
- Colby Ranger
In Hardware and Architecture
- Onur Mutlu
- Vivek Seshadri
- Michael A. Kozuch
- Todd C. Mowry
- Phillip B. Gibbons
- Gennady Pekhimenko
- Christos Kozyrakis
- Colby Ranger
Citations in the corpus
- Scaling the bandwidth wall: challenges in and avenues for CMP scaling (2009, background): “3x for the SPEC2k floating point benchmarks [1, 2, 3].”
- Base-delta-immediate compression: Practical data compression for on-chip caches (2012, methodology): “Simplicity, frequent occurrence in memory, and high compression ratio make repeated values an attractive target for a special consideration in data compression [2].”
- Evaluating MapReduce for Multi-core and Multiprocessor Systems (2007, methodology): “Such an optimization requires special hardware support [1, 13] not available in the systems we used.”