Microarchitectural techniques for power gating of execution units

By Zhigang Hu, Alper Buyuktosunoglu, Vijayalakshmi Srinivasan, V. Zyuban, H. Jacobson, Pradip Bose. 2004

439 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Young Geun Kim
2. Carole-Jean Wu
3. Udit Gupta
4. Gu-Yeon Wei
5. David M. Brooks

In Hardware and Architecture

1. Young Geun Kim
2. Gu-Yeon Wei
3. David M. Brooks
4. Carole-Jean Wu

In ML Systems & Hardware

1. Young Geun Kim
2. Carole-Jean Wu
3. Gu-Yeon Wei
4. David M. Brooks
5. Udit Gupta

Citations in the corpus

• Chasing Carbon: The Elusive Environmental Footprint of Computing (2020, background): “In addition to architectural innovations, circuit designers have enabled high-performance and low-power hardware through efforts that include clock/power gating [115], DVFS [116], and circuit-level timing speculation [117].”
• A brief survey on power gating design (2010, methodology): “generation (DSSG), compared to the fixed threshold technique in [4] which is called by them static sleep”