Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors
By Michael Zhang, Krste Asanovic. International Symposium on Computer Architecture, 2005
349 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/7adc7940bc250bab39c7823fbb1ef3f86fe0625a
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Doug Burger
- Naveen Muralimanohar
- Rajeev Balasubramonian
- Srini Devadas
- Saman P. Amarasinghe
- N. Jouppi
- S. Keckler
- Joel S. Emer
In Hardware and Architecture
- Rajeev Balasubramonian
- Doug Burger
- Naveen Muralimanohar
- Srini Devadas
- Saman P. Amarasinghe
- S. Keckler
- Joel S. Emer
- Lixin Zhang
Citations in the corpus
- Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, background): “Examples of ongoing research in these veins include [5, 6, 10, 11, 12, 15, 19, 20, 21, 22, 33, 44].”
- DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors (2018, background): “A review [3] of recent cache replacement and protection policies includes valuable commentary on less-cited excellent papers which have left little room for improvement [26, 27, 28, 45, 46, 59].”
- A NUCA Substrate for Flexible CMP Cache Sharing (2007, background): “Zhang and Asanovic [ 29 ] proposed the victim replication cache design, which selectively keeps copies of primary cache victims in each local L2 slice.”