POWER5 system microarchitecture

By B. Sinharoy, R. Kalla, Joel M. Tendler, R. Eickemeyer, J. Joyner. IBM Journal of Research and Development, 2005

329 citations recorded by the source corpus.

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Spatial Memory Streaming (2006, background): “, [16,29]), predicting regularly strided accesses to accelerate applications dominated by these simple access patterns.”
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (2008, background): “Note that, with an integrated memory controller (which is the industry trend as seen in IBM POWER5 [17, 39], Sun Nia-gara [22], AMD Athlon/Opteron [1], and Intel Nehalem [3]), it is relatively easy to communicate sequence numbers and whether a request is due to a load or store miss from the…”
Hybrid cache architecture with disparate memory technologies (2009, methodology): “a full system simulator [5] that has been validated against existing POWER5 hardware [25].”
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006, background): “Processors with two to eight cores are commercially available now [13, 19, 25].”
Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance (2009, unknown): “Hardware prefetch Four stream prefetchers per core [21]; 16 cache block prefetch distance and 2 prefetch degree On-chip caches 32KB 4-way L1 I/D caches with 1-cycle latency; 2MB, 16-way shared L2 cache with 11-cycle latency; all caches use LRU replacement and have 64B block size”