Detailed design and evaluation of redundant multi-threading alternatives

By Shubhendu S. Mukherjee, Michael Kontz, Steven K. Reinhardt. Proceedings 29th Annual International Symposium on Computer Architecture, 2002

538 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/6e96ca96f1069da8b84207fd4e14499bea533cdc

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In Computer Networks and Communications

In Electrical and Electronic Engineering

Citations in the corpus

Transient-fault recovery using simultaneous multithreading (2002, background): “A recent paper explores design options for fault detection via multithreading [6].”
Shoestring: probabilistic soft error reliability on the cheap (2010, background): “Other research has focused on providing fault protection using redundant multithreading [8, 17, 24, 27, 30] or hardware checkers like DIVA [6, 39].”
The soft error problem: an architectural perspective (2005, methodology): “Two broad solutions for fault detection include cycle-by-cycle lockstepping of identical processor pipelines [15] and redundant multithreading (RMT) [ 9 ][1].”
Characterizing the effects of transient faults on a high-performance processor pipeline (2004, background): “Other work related to the microarchitectural work presented here include higher overhead mechanisms to protect microprocessors with various forms of redundancy in microarchitecture [15, 18, 23].”
Design for soft error mitigation (2005, methodology): “The speed penalty of this approach is only 40% [ 26 ], but it is less flexible than the first approach as it requires some hardware modifications.”
Evaluating MapReduce for Multi-core and Multiprocessor Systems (2007, methodology): “To address this shortcoming, one should combine the Phoenix runtime with known error detection techniques [20, 21, 24].”
ReStore: symptom based soft error detection in microprocessors (2005, background): “Other work has introduced other forms of redundancy to mitigate the effects of soft errors [20, 24, 29].”
SWIFT: software implemented fault tolerance (2005, background): “[8] proposed a Chip-level Redundantly Threaded multiprocessor (CRT) and Gomaa et al.”