Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems

By Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt. ASPLOS XV, 2010

316 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

Memory scaling: A systems architecture perspective (2013, methodology): “To achieve these goals, we have designed various solutions including QoS-aware memory controllers [57, 58, 53, 32, 33, 54, 5, 69, 41, 23], interconnects [17, 18, 27, 28, 13, 59, 60, 19], and entire memory systems including caches, interconnect, and memory [22, 24, 19].”
Heracles: Improving resource efficiency at scale (2015, background): “There are several proposals for isolation and QoS features for memory controllers [30, 56, 32, 59, 57, 20, 40, 70].”
Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations (2011, unknown): “One direction that has attracted much research attention is the management of shared cache and bandwidth through techniques such as resource partitioning [4, 20, 27–34, 38], throttling [7] and adaptive cache replacement policies [14].”
MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms (2013, result): “proposed a cache controller level throttling mechanism [9], which is similar to our method in the sense that it effectively changes request rates.”
DORA: Optimizing Smartphone Energy Efficiency and Web Browser Performance under Interference (2018, background): “predict and operate processors at an optimal energy-efficient setting [21]–[31] but also allows designs to control the degree of memory interference experienced in a multiprogrammed setting [32]–[35].”