A novel architecture of the 3D stacked MRAM L2 cache for CMPs

By Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen. 2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009

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Evaluating STT-RAM as an energy-efficient main memory alternative (2013, methodology): “Per-bit energy consumption of memory operations normalized to the energy of accessing the row buffer for DRAM [41], [42] and STT-RAM memories [44], [57] TABLE III.”
Relaxing non-volatility for fast and energy-efficient STT-RAM caches (2011, methodology): “Other studies have used the predecessor to STT-RAM, MRAM, to design memory systems that take advantage of their low leakage [7], [20], [22].”
Hybrid cache architecture with disparate memory technologies (2009, background): “Another work studied SRAM-MRAM based hybrid cache to improve performance of pure MRAM based cache [27].”
Overcoming the challenges of crossbar resistive memory architectures (2015, background): “Researchers have looked at techniques such as early write termination [58], hybrid SRAM/STT-RAM architecture [50] and read-preemptive write-buffer designs [46] to mitigate the long write latency of STT-RAM.”