TOP-PIM: throughput-oriented programmable processing in memory

By Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Lifan Xu, Mike Ignatowski. IEEE International Symposium on High-Performance Parallel Distributed Computing, 2014

369 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/d78532d5add9d9751da025f05603c6fca04c8e07

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Citations in the corpus

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (2015, background): “More specifically, they focus on either accelerator architecture where its memory system is separate from the host processor’s main memory system (similar to a discrete GPU architecture) or the integration of and interaction between accelerators and DRAM using proprietary interfaces.”
RowHammer: A Retrospective (2019, neutral): “, [13]–[15], [18], [22], [24], [34]–[36], [56], [63], [72], [77], [78], [80], [91], [92], [95], [96], [99], [101], [102], [111], [121]–[123], [151], [153], [154], [160], [161], [172], [178], [179], [182], [195], [198], [215]–[219], [221], [222], [228], [257], and [260]).”
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning (2017, background): “Driven by the data intensive applications and the 3D-stacking technology, PIM or near data computing is resurgent, with lots of industry effort [55, 56].”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “The second approach takes advantage of the design of emerging 3D-stacked memory technologies to enable PIM in a more general-purpose manner [7, 34, 35, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 72, 73, 74, 75, 77, 87, 88, 89, 91].”
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, positive): “Recent efforts [2], [3], [4], [5], [58] decouple logic and memory designs in different dies, adopting 3D stacked memories with a logic layer that encapsulates processing units to perform computation, as shown in Figure 3(b).”
DRISA: A DRAM-based Reconfigurable In-Situ Accelerator (2017, background): “plenty of recent work on PIM [10, 12, 16, 18, 20, 30, 32, 34, 36, 42, 46, 52, 53, 67, 73, 73, 75, 76, 88, 93, 95] that built lightweight processors, reconfigurable or application-specific logics in the logic die of HMC [74] or HBM [58].”
A scalable processing-in-memory accelerator for parallel graph processing (2015, methodology): “[61] proposed to integrate GPGPUs with 3Dstacked DRAM for in-memory computing.”