Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement

By Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Hai Helen Li, Yiran Chen. 2008 45th ACM/IEEE Design Automation Conference, 2008

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Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Several prior works have proposed the use of STT technology [29], [35] to reduce energy consumption of the processor and caches [17], [20], [27], [53], [56], [57], [62], [67].”
A durable and energy efficient main memory using phase change memory technology (2009, background): “The cell area for DRAM, PCM and STT-RAM are 6F 2 [25], 5∼8F 2 [14], and 37∼40F 2 [7] respectively, where F is the feature size.”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, background): “Some recent work [10, 12] has evaluated the benefits of MRAM as a universal memory replacement for L2 caches and main memories in single-core chips.”
Hybrid cache architecture with disparate memory technologies (2009, methodology): “All cache parameters used in this study were obtained either from CACTI [23] or its modified versions [10]and are shown in Table 2.”
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory (2012, methodology): “For example, Smullen et al. relaxed the retention time requirement to improve the timing and energy profile of STT-RAMs [16].”