Hybrid cache architecture with disparate memory technologies

By Xiaoxia Wu, Jian Li, Lixin Zhang, W. Speight, Ramakrishnan Rajamony, Yuan Xie. International Symposium on Computer Architecture, 2009

380 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Yet, STT-RAM technology has so far only been explored as an SRAM substitute for on-chip caches [27], [53], [56], [57], [62], but has not been considered as a candidate for main memory.”
Phase-Change Technology and the Future of Main Memory (2010, background): “(Related work also supports this effort.(23,24)) The proposed memory architecture lays the foundation for exploiting PCM scalability and nonvolatility in main memory.”
Trends in big data analytics (2014, methodology): “NVM could also be used to implement additional caching levels [96,84], or to replace the persistent store [27], thus facilitating the collapse of memory hierarchies—a single memory type to be used at various levels.”
Relaxing non-volatility for fast and energy-efficient STT-RAM caches (2011, methodology): “Other studies have used the predecessor to STT-RAM, MRAM, to design memory systems that take advantage of their low leakage [7], [20], [22].”