Benchmarking nanotechnology for high-performance and low-power logic transistor applications

By R. Chau. IEEE transactions on nanotechnology, 2004

671 citations recorded by the source corpus.

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices (2006, background): “conservative normalization could be due to the perimeter of the wire [19]—divide reported current values by π.”
Scaling Behaviors of Graphene Nanoribbon FETs: A Three-Dimensional Quantum Simulation Study (2007, methodology): “We compute the intrinsic delay as τ = (Qon − Qoff)/Ion, where Qon and Qoff are the total charge in the channel at ON-state and OFF-state, respectively, and Ion is the on-current [15].”
A Graphene Field-Effect Device (2007, background): “One of the most promising future options to enhance silicon is the introduction of carbon-based electronics [3].”
Nanowire Transistor Performance Limits and Applications (2008, methodology): “The performance of the Ge/Si nanowire devices have also been compared to planar Si devices using the intrinsic gate delay benchmark [82], τ = CV/I , where C is the gate capacitance, V = Vdd, and I is the on current Ion.”