Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors

By Onur Mutlu, Thomas Moscibroda. Micro, 2007

599 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/3ef44315caebb6169b7ffbf9886cd782193ab40e

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In Electrical and Electronic Engineering

In Hardware and Architecture

Citations in the corpus

Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013, background): “[4, 9, 23, 22, 32, 31]), to mitigate inter-application interference and queueing latencies in multi-core systems.”
RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing (2019, unknown): “from the thread-level memory scheduler [61].”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “As a result, requests of an application that could have otherwise hit in the row-buffer will miss in the row-buffer, signiﬁcantly degrading the performance of the application (and potentially the overall system) [37, 40, 56, 67].”
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, methodology): “We report performance using weighted speedup [42, 43], a commonly-used metric to evaluate the performance of a multi-application workload [15, 38, 39, 68, 71, 72, 86, 88, 89, 124, 125, 132].”
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (2010, methodology): “In fact, STFM has difficulty distinguishing between weights 4, 5, and 6 because controllers are not coordinated; a thread with higher weight can be better prioritized in one controller than in another.”
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008, methodology): “Previous research [28, 22, 25] experimentally demonstrate d the unfairness of FR-FCFS and proposed new scheduling policies th at are fairer and that provide QoS to different threads.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “, due to the ever-increasing need to process large amounts of data at real time, and predictable performance continues to be a critical concern in the design of modern computing systems [2, 16, 117, 118, 119, 120, 121, 122, 123], it is increasingly critical to design low-latency main memory chips.”
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (2008, methodology): “QoS-aware memory controllers were recently proposed [29, 31, 34] to provide fair access to threads sharing the DRAM system.”
RAIDR: Retention-aware intelligent DRAM refresh (2012, background): “This unintuitive result occurs because while the common FR-FCFS memory scheduling policy maximizes memory throughput, it does not necessarily maximize system performance; applications with high row hit rates can starve applications with low row hit rates [34, 35].”
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, methodology): “We compare TCM’s performance against four previously proposed memory scheduling algorithms, FRFCFS [19], STFM [13], PAR-BS [14] (best previous algorithm for fairness) and ATLAS [5] (best previous algorithm for system throughput).”
Memory scaling: A systems architecture perspective (2013, methodology): “To achieve these goals, we have designed various solutions including QoS-aware memory controllers [57, 58, 53, 32, 33, 54, 5, 69, 41, 23], interconnects [17, 18, 27, 28, 13, 59, 60, 19], and entire memory systems including caches, interconnect, and memory [22, 24, 19].”
Evaluating STT-RAM as an energy-efficient main memory alternative (2013, methodology): “DRAM operation is described in more detail in [25], [28], [31], [45].”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, unknown): “Our technique, Fairness via Source Throttling (FST), estimates the unfairness in the entire shared memory system.”
Reducing memory interference in multicore systems via application-aware memory channel partitioning (2011, background): “We present a brief background about the DRAM main memory syst em; more details can be found in [6, 16, 22].”
NoHype: virtualized cloud infrastructure without the virtualization (2010, background): “As this interaction is extremely limited (no information is passed and the required function is extremely simple), the vulnerability that is opened is very limited (though, still not ideal).”
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013, background): “This problem also becomes more severe with core scaling and the increase in the number of simultaneously executing threads [24], in a way that is similar to the memory bandwidth problem in multi-core systems [38, 42].”