Memory scaling: A systems architecture perspective

By Onur Mutlu. 2013 5th IEEE International Memory Workshop, 2013

296 citations recorded by the source corpus.

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques. In this paper, after describing the demands and challenges faced by the memory system, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we survey three key solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system, 2) designing a memory system that employs emerging memory technologies and takes advantage of multiple different technologies, 3) providing predictable performance and QoS to applications sharing the memory system. We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory.

Subfields: Computer Networks and Communications, Hardware and Architecture, Information Systems

View Paper: https://www.semanticscholar.org/paper/ad2272bb32caee5fadfab633e202d92ffde120c4

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Hardware and Architecture

In Information Systems

Citations in the corpus

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014, background): “As DRAM process technology scales down to smaller feature sizes, we hope that our findings will enable new system-level [51] approaches to enhance DRAM reliability.”
Retrospective: Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors (2023, unknown): “We believe system-DRAM cooperation [14, 52] will be important to enabling complete solutions.”
Ramulator: A Fast and Extensible DRAM Simulator (2016, unknown): “We hope that Ramulator would facilitate DRAM research in an era when main memory is undergoing rapid changes [23], [31].”
RowHammer: A Retrospective (2019, methodology): “, [56], [57], [59], [97], [112]–[116], [124]–[126], [128], [132], [145]–[147], [149], [158], [159], [163], [173], [181], [201], [203], [215]–[217], [229]–[231], [235], [236], and [250]).”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “As low-latency computing is becoming ever more important [1], e.”
Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives (2017, background): “As DRAM scales to smaller technology nodes, its error rate continues to increase [94, 123, 135, 136, 139] and effects like read disturb [94], cell-to-cell interference [80–83, 112, 154], and variable retention time [80, 112, 154, 158] become more severe [94, 135, 136, 139].”
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery (2015, background): “take advantage of these characteristics [37][38][40][41][42], retention charac-”