Reducing memory interference in multicore systems via application-aware memory channel partitioning

By Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Taylan Kandemir, Thomas Moscibroda. Micro, 2011

298 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/429e32dfe26a53273d8b1cfd5ce5dad3d962bb02

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In Computer Networks and Communications

In Hardware and Architecture

Citations in the corpus

MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, methodology): “We report performance using weighted speedup [42, 43], a commonly-used metric to evaluate the performance of a multi-application workload [15, 38, 39, 68, 71, 72, 86, 88, 89, 124, 125, 132].”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, background): “…movement consumes a significant fraction of the total workload energy, (3) it is memory-intensive (i.e., its last-level cache misses per kilo instruction , or MPKI, is greater than 10 [21, 83, 84, 103]), and (4) data movement is the single largest component of the function’s energy consumption.”
Memory scaling: A systems architecture perspective (2013, methodology): “To achieve these goals, we have designed various solutions including QoS-aware memory controllers [57, 58, 53, 32, 33, 54, 5, 69, 41, 23], interconnects [17, 18, 27, 28, 13, 59, 60, 19], and entire memory systems including caches, interconnect, and memory [22, 24, 19].”
Heracles: Improving resource efficiency at scale (2015, background): “Despite significant research on memory bandwidth isolation [30, 56, 32, 59], there are no hardware isolation mechanisms in commercially available chips.”
Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Further, data accesses originating from different cores can interleave in any fashion which can cause the memory row buffer locality to degrade [4], [43], [46], [65].”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “, [6, 16, 23, 24, 38, 40, 41, 43]) that prioritize certain favorable requests in the memory controller to improve system performance and/or fairness.”
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance (2013, background): “Several memory request scheduling [3, 12, 26, 27, 33–35, 41, 50, 58, 59] and data partitioning [20, 40, 57] techniques have been proposed to improve one or both within the context of multi-core, GPGPU, and heterogeneous CPU-GPU systems [3].”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, unknown): “2011b] and using channel partitioning [Muralidhara et al. 2011], and we leave this for future work”
RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013, background): “, row or cache line interleaving [39]) have this property.”