Limits to binary logic switch scaling - a gedanken model

By Victor V. Zhirnov, Ralph K. Cavin III, James A. Hutchby, George Bourianoff. Proceedings of the IEEE, 2003

479 citations recorded by the source corpus.

Subfields: Artificial Intelligence, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/a4ade235a98c7380122759e6f53038342c764a62

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In Artificial Intelligence

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Igor L. Markov

Citations in the corpus

Nanoionics-based resistive switching memories. (2007, background): “One ultimate limit will be given by the tunnelling distance between neighbouring cells as well as the leakage current from the word and bit line, again potentially dominated by tunnellin”
In search of "Forever," continued transistor scaling one new material at a time (2005, background): “Fortunately, the limits for a 30-nm planar Si MOSFET are caused by materials and the device structure and are not hard quantum mechanical limits [20],”
Energy-Efficient Single Flux Quantum Technology (2011, background): “It is argued that even if entirely different electron transport devices are invented for digital logic, they will not exceed the performance and integration densities obtainable with CMOS [4].”
Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits (2015, background): “I. INTRODUCTION SUCCESSFUL scaling of CMOS field-effect transis-tors (FETs) has occurred over more than four decades according to the cadence of Moore’s law [1] and has now reached gate lengths of 20 nm in [2].”
Synthesis of quantum-logic circuits (2004, unknown): “A quantitative analysis of these phenomena leads experts from NCSU, SRC and Intel [36] to derive fundamental limitations on the scalability of any computing device which moves electrons.”
Thermal Interface Materials: Historical Perspective, Status, and Future Directions (2006, background): “The projections for heat generation from the chip indicate that both the total power (Q )a nd the heat flux (q )a re going to increase [ 7 ].”
Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking (2013, background): “From the ITRS projections it is apparent that the scaling will be influenced by fundamental physical limits of device switching [2].”
Limits on fundamental limits to computation (2014, background): “The study in [63] explores a general binary-logic switch model with binary states represented by two quantum wells separated by a potential barrier .”
Silicon CMOS devices beyond scaling (2006, background): “Why is this so much larger than Zhirnov’s limit [56]? First, the assumption for m (Zhirnov assumed m ¼ m0); next, our assumption of the equality of tunneling and thermionic emission currents, whereas Zhirnov assumed an almost transparent barrier [ 56 ]; and finally the use of a parabolic rather than”