Device scaling limits of Si MOSFETs and their application dependencies

By D. Frank, R. Dennard, Edward J. Nowak, P. Solomon, Yuan Taur, H.-S.P. Wong. Proceedings of the IEEE, 2001

1,599 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/cb29f6cfda786c66766056e3b35fda630395934c

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Citations in the corpus

2D materials for spintronic devices (2020, methodology): “Graphene, a hexagonal 2D arrangement of sp(2)-bonded carbon atoms, may be uniquely suited for this purpose due to its (1) relatively long spin diffusion length and lifetime (theoretically predicted, and experimentally being examined) and (2) ability to be readily interfaced with other classes of mat”
Scaling of Nanowire Transistors (2008, background): “As scaling of conventional bulk MOSFETs [14] is approaching the limit [15], [16] imposed by gate oxide tunneling, body doping, band-to-band tunneling, etc.”
Physical limits of silicon transistors and circuits (2005, background): “The more thoughtful assessments have been the subject of a good number of excellent reviews (Thompson et al 1998, Frank et al 2001, Meindl et al 2001, Plummer and Griffin 2001, Solomon et al 2002).”
A continuous, analytic drain-current model for DG MOSFETs (2004, background): “As CMOS scaling is approaching the limit imposed by gate oxide tunneling, double-gate (DG) MOSFET is becoming an intense subject of very large-scale integration (VLSI) research because in theory it can be scaled to the shortest channel length possible for a given gate oxide thickness [ 3 ].”
High-performance carbon nanotube field-effect transistor with tunable polarities (2005, background): “CMOS in sight [16], carbon nanotubes show great promise among the materials investigated so far for post-Si technology.”
Nanoelectronics from the bottom up. (2007, methodology): “But as device features are pushed towards the deep sub-100-nm regime, the conventional scaling methods of the semiconductor industry face increasing technological and fundamental challenge”
Experimental Review of Graphene (2011, background): “However, as the size of the device is re- duced, more and more issues (commonly known as short channel effects) begin to appear (Frank et al., 2001).”
FinFETs and Other Multi-Gate Transistors (2007, neutral): “Extended Abstracts of the International Conference on Solid State Devices and Materials (SSDM), 68 (2002) 59 B.S. Doyle, S. Datta, M. Doczy, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, R. Chau: High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Letters 24-4, 26”
Colloquium: Strong-field phenomena in periodic systems (2017, background): “While firstgeneration semiconductor devices were based on a diffusive transport, today’s nano-MOSFETs (metal-oxide-semiconductor field-effect transistor) operate in the quasiballistic and highfield regimes (Datta, 2012; Frank et al., 2001; Martin et al., 2004; Palestri et al., 2005).”
Silicon CMOS devices beyond scaling (2006, methodology): “Some confusion has been caused by notation, since the scale length, K, is p times the attenuation length, so that Frank’s criterion [25] of channel length greater than 1.”
Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs (2007, background): “S BULK CMOS scaling [ 1 ], [2] is approaching the limit that is imposed by gate oxide tunneling, body doping, band-to-band tunneling, etc., multiple-gate MOSFETs [3] have been proposed to scale down CMOS technology more aggressively.”
In search of "Forever," continued transistor scaling one new material at a time (2005, background): “The minimum SiO thickness is limited by tunneling currents and has previously been discussed [32].”